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[VHDL-FPGA-Verilog] xiyiji

Description: 洗衣机控制器，包括清洗、漂水、脱水等状态，vhdl-washing machine controller, including cleaning, bleaching water, dehydration state, vhdl
Platform: | Size: 4096 | Author: 飘来的南风 | Hits:

[Other] VERlog

Description: 不错的VHDL讲义?淮淼腣HDL讲义-good VHDL overhead good VHDL overhead
Platform: | Size: 234496 | Author: | Hits:

[VHDL-FPGA-Verilog] VerilogHDLchinapub

Description: Verilog HDL硬件描述语言 01简介.PDF 02HDL指南.PDF 03语言要素.PDF 04表达式.PDF 05门电平模型化.PDF 06用户定义原语.PDF 07数据流模型化.PDF 08行为建模.PDF 09结构建模.PDF 10其它论题.PDF 11验证.PDF 12建模实例.PDF 13语法参考.PDF-Verilog HDL Hardware Description Language Introduction 01. PDF 02HDL Guide. PDF 0 3 language elements. PDF 04 expressions. PDF 05-level modeling. PDF 06 user-defined primitives. P DF 07 data flow modeling. PDF 08 behavior modeling. PDF 09 modeling structure. PDF 10 other topics . PDF 11 certification. PDF 12 model. PDF 13 syntax reference. PDF
Platform: | Size: 4837376 | Author: 高 | Hits:

[Software Engineering] VHDL_PLL

Description: 介绍了锁相环PLL的实现原理，可以为VHDL实现PLL提供参考。-introduced PLL PLL The principle for VHDL PLL reference.
Platform: | Size: 96256 | Author: CGT | Hits:

[Communication-Mobile] my_pll

Description: VHDL程序，使用锁相法实现位同步的算法，并可以对算法进行仿真-VHDL, the use of lock-in-law to achieve the synchronization algorithm, the algorithm can be simulated
Platform: | Size: 1024 | Author: 笑容 | Hits:

[VHDL-FPGA-Verilog] 20040810319xiyijiVHDL

Description: 自己 写的课程设计 ，用vhdl写的模拟洗衣机，希望对大家有帮助-himself wrote the curriculum design, simulation vhdl wrote washing machines, we hope to help
Platform: | Size: 1317888 | Author: 伍杰 | Hits:

[VHDL-FPGA-Verilog] FreqCounter

Description: 一个有效位为4位的十进制的数字频率计,VHDL语言编写，已在硬件实验箱上实验通过。-an effective place to four the number of decimal frequency meter, VHDL language, in the box on the experimental hardware experiment.
Platform: | Size: 3072 | Author: 小花猫 | Hits:

[VHDL-FPGA-Verilog] uart1

Description: 串口程序，基于VHDL 的，很好的程序 快下吧-Serial procedures, based on VHDL, and a very good program, are you fast
Platform: | Size: 577536 | Author: 张俊 | Hits:

[VHDL-FPGA-Verilog] pinlvji

Description: 频率计，vhdl语言， ispDesignEXPERT-Frequency meter, vhdl language, ispDesignEXPERT
Platform: | Size: 1024 | Author: yuankui | Hits:

[VHDL-FPGA-Verilog] PS2

Description: 使用XLINX的FPGA实现P/S2的键盘接口-The FPGA using XLINX realize P/S2 keyboard interface
Platform: | Size: 3072 | Author: toneytang | Hits:

[Software Engineering] FPGA

Description: 基于VHDL语言 智力抢答器的设计 本人的课程设计-Based on the VHDL language design intellectual Answer my curriculum design
Platform: | Size: 489472 | Author: 滕莹 | Hits:

[VHDL-FPGA-Verilog] bmul32

Description: 用VHDL写的一个32位并行乘法器的源代码，已经过验证，可以直接使用-Use VHDL to write a 32-bit parallel multiplier source code, has already been verified, you can directly use
Platform: | Size: 1024 | Author: zh | Hits:

[Communication-Mobile] miniuart

Description: vhdl实现miniUART代码 分模块设计和状态机设计,内核超级小-VHDL code miniUART to achieve sub-module design and state machine design, super small kernel
Platform: | Size: 90112 | Author: harrybird | Hits:

[VHDL-FPGA-Verilog] FPGA_27examples

Description: FPGA技术中，VHDL程序是很重要的一部分，这里收集了一些重要的典型模块，可以参考。
Platform: | Size: 1278976 | Author: 崔易 | Hits:

[VHDL-FPGA-Verilog] electroclock

Description: VHDL的数字钟，内含各个模块的源程序，可直接运行-VHDL digital clock, each module contains the source code can be run directly
Platform: | Size: 82944 | Author: 玉峰 | Hits:

[VHDL-FPGA-Verilog] PWM

Description: 利用VHDL语言实现FPGA的PWM输出波形，占空比可控-FPGA using VHDL language realize the PWM output waveform, duty cycle controlled
Platform: | Size: 36864 | Author: 王传辉 | Hits:

[VHDL-FPGA-Verilog] Edition

Description: VHDL可重用英文书,书中有许多对VHDL可重用的具体介绍,是一般的相关书籍所没有的.-VHDL reusable English book has a lot of reusable VHDL specific introduction is generally not related books.
Platform: | Size: 4564992 | Author: 徐民 | Hits:

[VHDL-FPGA-Verilog] B_to_D

Description: 用VHDL语言将二进制数据转换成十进制数据，并将十进制的每一个位分离出来单独存放。使用状态机实现，程序简单，仿真效果很理想，占用可编程器件的资源较少。-VHDL language with the binary data into decimal data and decimal places separated from each store individually. Realize the use of state machine, the program is simple, simulation results are satisfactory, occupation of programmable devices have fewer resources.
Platform: | Size: 1024 | Author: yato_logo | Hits:

[matlab] FractionalPLLDesign

Description: 是关于sigma delta PLL设计的详细论文，论文中有具体的设计细节，并在附录中有相应的matlab、vhdl code-Is about the design of sigma delta PLL detailed papers, papers in the specific design details, and in the appendix corresponding matlab, vhdl code
Platform: | Size: 3802112 | Author: xin | Hits:

[VHDL-FPGA-Verilog] ssz

Description: 数字钟，用VHDL写的各个模块，顶层用图形编辑，在实验箱上完全通过-Digital clock, using VHDL written by various modules, top-level graphics editing, in the experimental box completely through
Platform: | Size: 257024 | Author: kevin liu | Hits:
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